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-- Company:
-- Engineer:
--
-- Create Date: 11:28:58 09/29/05
-- Design Name:
-- Module Name: FourDisplaySevenSegVHDL - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FourDisplaySevenSegVHDL is
Port ( clk : in std_logic;
Digit3 : in std_logic_vector(4 downto 0); -- MSB is to control the decimal
Digit2 : in std_logic_vector(4 downto 0);
Digit1 : in std_logic_vector(4 downto 0);
Digit0 : in std_logic_vector(4 downto 0);
InvertDigit : in std_logic;
InvertDriver : in std_logic;
SegDriver : out std_logic_vector(7 downto 0); -- sega is 0, segg is 6, segDec is 7
DisplayDriver : out std_logic_vector(3 downto 0) -- drives the cathode of each display
);
end FourDisplaySevenSegVHDL;
architecture Behavioral of FourDisplaySevenSegVHDL is
signal Delay : std_logic_vector(15 downto 0);
signal Sel : std_logic_vector(1 downto 0); -- used to select which display data goes to
signal data : std_logic_vector(4 downto 0);
signal segs : std_logic_vector(7 downto 0);
signal displaysel : std_logic_vector (3 downto 0);
begin
process(clk)
begin
if(InvertDigit = '1') then
SegDriver <= not segs;
else
SegDriver <= segs;
end if;
if(InvertDriver = '1') then
DisplayDriver <= not Displaysel;
else
DisplayDriver <= Displaysel;
end if;
end process;
-- drives a delay counter to toggle the displays at 762 hz
process(clk)
begin
if(clk = '1' and clk'event) then
Delay <= Delay + 1;
end if;
end process;
-- when the delay clock overflows, change our display select
process(clk)
begin
if(clk = '0' and clk'event and Delay = "0000000000000000") then
Sel <= Sel + 1;
end if;
end process;
-- MUX to send dat to the display decoder
with Sel select
Data <= Digit3 when "11",
Digit2 when "10",
Digit1 when "01",
Digit0 when "00",
Digit0 when others;
-- basically a 2 to 4 decoder to drive each display
with sel select
displaysel <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11",
"0000" when others;
-- seven seg decoder with decimal
with data select
segs <= "00111111" when "00000",
"00000110" when "00001",
"01011011" when "00010",
"01001111" when "00011",
"01100110" when "00100",
"01101101" when "00101",
"01111101" when "00110",
"00000111" when "00111",
"01111111" when "01000",
"01101111" when "01001",
"01110111" when "01010",
"01111100" when "01011",
"00111001" when "01100",
"01011110" when "01101",
"01111001" when "01110",
"01110001" when "01111",
"10111111" when "10000",
"10000110" when "10001",
"11011011" when "10010",
"11001111" when "10011",
"11100110" when "10100",
"11101101" when "10101",
"11111101" when "10110",
"10000111" when "10111",
"11111111" when "11000",
"11101111" when "11001",
"11110111" when "11010",
"11111100" when "11011",
"10111001" when "11100",
"11011110" when "11101",
"11111001" when "11110",
"11110001" when "11111",
"00000000" when others;
end Behavioral;