-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:39:38 10/07/05 -- Design Name: -- Module Name: VGA_DigitDisplayVHDL - Behavioral -- Project Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity VGA_DigitDisplayVHDL is Port ( clk : in std_logic; row : in std_logic_vector(8 downto 0); column : in std_logic_vector(9 downto 0); color : in std_logic_vector(2 downto 0); TopRow1 : in std_logic_vector(8 downto 0); LeftColumn1 : in std_logic_vector(9 downto 0); fill : IN std_logic; red : OUT std_logic; green : OUT std_logic; blue : OUT std_logic; Data : in std_logic_vector(5 downto 0)); end VGA_DigitDisplayVHDL; architecture Behavioral of VGA_DigitDisplayVHDL is COMPONENT vga_boxvhdl PORT( clk : IN std_logic; Row : IN std_logic_vector(8 downto 0); Column : IN std_logic_vector(9 downto 0); TopRow : IN std_logic_vector(8 downto 0); LeftColumn : IN std_logic_vector(9 downto 0); Height : IN std_logic_vector(8 downto 0); Width : IN std_logic_vector(9 downto 0); Fill : IN std_logic; Video : OUT std_logic ); END COMPONENT; signal segaout : std_logic; signal segbout : std_logic; signal segcout : std_logic; signal segdout : std_logic; signal segeout : std_logic; signal segfout : std_logic; signal seggout : std_logic; signal seghout : std_logic; signal segiout : std_logic; signal toprow : std_logic_vector(8 downto 0); signal leftcolumn : std_logic_vector(9 downto 0); signal segon : std_logic_vector(8 downto 0); signal segaRow : std_logic_vector(8 downto 0); signal segaColumn : std_logic_vector(9 downto 0); signal segbRow : std_logic_vector(8 downto 0); signal segbColumn : std_logic_vector(9 downto 0); signal segcRow : std_logic_vector(8 downto 0); signal segcColumn : std_logic_vector(9 downto 0); signal segdRow : std_logic_vector(8 downto 0); signal segdColumn : std_logic_vector(9 downto 0); signal segeRow : std_logic_vector(8 downto 0); signal segeColumn : std_logic_vector(9 downto 0); signal segfRow : std_logic_vector(8 downto 0); signal segfColumn : std_logic_vector(9 downto 0); signal seggRow : std_logic_vector(8 downto 0); signal seggColumn : std_logic_vector(9 downto 0); signal seghRow : std_logic_vector(8 downto 0); signal seghColumn : std_logic_vector(9 downto 0); signal segiRow : std_logic_vector(8 downto 0); signal segiColumn : std_logic_vector(9 downto 0); begin toprow <= toprow1; leftcolumn <= leftcolumn1; red <= color(0) and ((segaout and segon(8)) or (segbout and segon(7)) or (segcout and segon(6)) or (segdout and segon(5)) or (segeout and segon(4)) or (segfout and segon(3)) or (seggout and segon(2)) or (seghout and segon(1)) or (segiout and segon(0))); blue <= color(2) and ((segaout and segon(8)) or (segbout and segon(7)) or (segcout and segon(6)) or (segdout and segon(5)) or (segeout and segon(4)) or (segfout and segon(3)) or (seggout and segon(2)) or (seghout and segon(1)) or (segiout and segon(0))); green <= color(1) and ((segaout and segon(8)) or (segbout and segon(7)) or (segcout and segon(6)) or (segdout and segon(5)) or (segeout and segon(4)) or (segfout and segon(3)) or (seggout and segon(2)) or (seghout and segon(1)) or (segiout and segon(0))); with data select segon <= "111111000" when "000000", -- 0 "011000000" when "000001", -- 1 "110110010" when "000010", -- 2 "111100010" when "000011", -- 3 "011001010" when "000100", -- 4 "101101010" when "000101", -- 5 "101111010" when "000110", -- 6 "111000000" when "000111", -- 7 "111111010" when "001000", -- 8 "111101010" when "001001", -- 9 "111011010" when "001010", -- a "001111010" when "001011", -- b "100111000" when "001100", -- c "011110010" when "001101", -- d "100111010" when "001110", -- e "100011010" when "001111", -- f "111101010" when "010000", -- g "001011010" when "010001", -- h "000011000" when "010010", -- i "011110000" when "010011", -- j "001011110" when "010100", -- k "000111000" when "010101", -- l "001010011" when "010110", -- m "001010010" when "010111", -- n "001110010" when "011000", -- o "110011010" when "011001", -- p "111001000" when "011010", -- q "110011011" when "011011", -- r "101101010" when "011100", -- s "100000101" when "011101", -- t "001110000" when "011110", -- u "001110000" when "011111", -- v "011111001" when "100000", -- w "011011010" when "100001", -- x "011101010" when "100010", -- y "110110010" when "100011", -- z "000000000" when others; process(clk) begin segarow <= TopRow + "000000000"; segacolumn <= LeftColumn + "0000000000"; segbrow <= TopRow + "000000101"; segbcolumn <= LeftColumn + "0000001111"; segcrow <= TopRow + "000011001"; segccolumn <= LeftColumn + "0000001111"; segdrow <= TopRow + "000101101"; segdcolumn <= LeftColumn + "0000000000"; segerow <= TopRow + "000011001"; segecolumn <= LeftColumn + "0000000000"; segfrow <= TopRow + "000000101"; segfcolumn <= LeftColumn + "0000000000"; seggrow <= TopRow + "000000101"; seggcolumn <= LeftColumn + "0000001000"; seghrow <= TopRow + "000010110"; seghcolumn <= LeftColumn + "0000000101"; segirow <= TopRow + "000011011"; segicolumn <= LeftColumn + "0000001000"; end process; Sega: vga_boxvhdl PORT MAP( clk => clk, Row => row, Column => column, TopRow => segarow, LeftColumn => segacolumn, Height => "000000101", Width => "0000010100", Fill => fill, Video => segaout ); Segb: vga_boxvhdl PORT MAP( clk => clk, Row => row, Column => column, TopRow => segbrow, LeftColumn => segbcolumn , Height => "000010100", Width => "0000000101", Fill => fill, Video => segbout ); Segc: vga_boxvhdl PORT MAP( clk => clk, Row => row, Column => column, TopRow => segcrow, LeftColumn => segccolumn, Height => "000010100", Width => "0000000101", Fill => fill, Video => segcout ); Segd: vga_boxvhdl PORT MAP( clk => clk, Row => row, Column => column, TopRow => segdrow, LeftColumn => segdcolumn, Height => "000000101", Width => "0000010100", Fill => fill, Video => segdout ); Sege: vga_boxvhdl PORT MAP( clk => clk, Row => row, Column => column, TopRow => segerow, LeftColumn => segecolumn, Height => "000010100", Width => "0000000101", Fill => fill, Video => segeout ); Segf: vga_boxvhdl PORT MAP( clk => clk, Row => row, Column => column, TopRow => segfrow, LeftColumn => segfcolumn, Height => "000010100", Width => "0000000101", Fill => fill, Video => segfout ); Segg: vga_boxvhdl PORT MAP( clk => clk, Row => row, Column => column, TopRow => seggrow, LeftColumn => seggcolumn, Height => "000010001", Width => "0000000100", Fill => fill, Video => seggout ); Segh: vga_boxvhdl PORT MAP( clk => clk, Row => row, Column => column, TopRow => seghrow, LeftColumn => seghcolumn, Height => "000000101", Width => "0000001010", Fill => fill, Video => seghout ); Segi: vga_boxvhdl PORT MAP( clk => clk, Row => row, Column => column, TopRow => segirow, LeftColumn => segicolumn, Height => "000010010", Width => "0000000100", Fill => fill, Video => segiout ); end Behavioral;