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-- Company:
-- Engineer:
--
-- Create Date: 17:01:39 09/23/05
-- Design Name:
-- Module Name: VGA_controller2 - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity VGA_controller2 is
Port ( clk : in std_logic;
HSync : out std_logic;
VSync : out std_logic;
Video_Enable : out std_logic;
Pixel_Pos : out std_logic_vector(9 downto 0);
Row_Pos : out std_logic_vector(8 downto 0));
end VGA_controller2;
architecture Behavioral of VGA_controller2 is
signal pxc : std_logic;
signal es : std_logic;
signal hsc : std_logic_vector (9 downto 0) := "0000000000";
signal hsctc : std_logic;
signal vsc : std_logic_vector (9 downto 0) := "0000000000";
signal vsctc : std_logic;
signal ven : std_logic := '0';
signal hs : std_logic := '1';
signal vs : std_logic :='1';
signal pc : std_logic_vector(9 downto 0) := "0000000000";
signal rc : std_logic_vector(8 downto 0) := "000000000";
begin
-- this makes sure that the outputs
-- are updated properly
VSync <= vs;
HSync <= hs;
Video_Enable <= ven;
Pixel_Pos <= pc;
Row_Pos <= rc;
-- this process generates the PiXel Clock
-- this is a 25 mhz signal used to break
-- the system clock up into 4 distinct event times
-- (this is done with the help of ES)
process(clk)
begin
if(clk = '1' and clk'event) then
pxc <= not pxc;
end if;
end process;
-- this process generates the Enable Sync clock
-- ES is a 25 mhz clock, 90 degrees out of phase
-- with the pxc)
process(clk)
begin
if(clk = '0' and clk'event) then
es <= not es;
end if;
end process;
-- this process will maintain the Horizontal
-- Sync Counter. the counter will be updates
-- on the falling edge of the system clock
-- and when pxc = 1
process(clk)
begin
if(clk = '0' and clk'event and pxc = '1') then
if(hsc < "1100011111") then -- 799
hsc <= hsc + 1;
hsctc <= '0';
-- elsif(hsc = "1100011110") then -- 798
-- hsc <= hsc + 1;
-- hsctc <= '1';
else
hsc <= "0000000000";
hsctc <= '1';
end if;
end if;
end process;
-- this process will maitain the Vertical Sync
-- counter. this counter will be updated on the
-- falling edge of the system clock and when
-- pxc = '0' and hsctc = '1'
process(clk)
begin
if(clk = '0' and clk'event and pxc = '0') then
if(hsctc = '1') then
if(vsc < "1000001000") then -- 520
vsc <= vsc + 1;
vsctc <= '0';
--elsif(vsc = "1000001000") then-- 520
-- vsc <= vsc + 1;
-- vsctc <= '1';
else
vsc <= "0000000000";
vsctc <= '1';
end if;
end if;
end if;
end process;
-- this process will generate the HS pulse
-- it will be low for 96 pixel clock cycles
process(clk)
begin
if(clk = '0' and clk'event and pxc = '0') then
if(hsc < "0001100000") then -- 96
hs <= '0';
else
hs <= '1';
end if;
end if;
end process;
-- this process will generate the VS pulse
process(clk)
begin
if(clk = '0' and clk'event and pxc = '1') then
if(vsc < "0000000010") then --2
vs <= '0';
else
vs <= '1';
end if;
end if;
end process;
-- this process will generate the video enable signal
process(clk)
begin
if(clk = '1' and clk 'event and es = '1') then
if(hsc > "0010010000" and hsc < "1100010000" and vsc > "0000011111" and vsc < "0111111111") then
ven <= '1';
else
ven <= '0';
end if;
end if;
end process;
-- this process generates the pixel count
process(clk)
begin
if(clk = '0' and clk'event and pxc = '1') then
if(ven = '1') then
pc <= pc + 1;
else
pc <= "0000000000";
end if;
end if;
end process;
-- this process will generate the row count
process(clk)
begin
if(clk = '0' and clk'event and pxc = '0' and hsctc = '1') Then
if(vsc > "0000011111" and vsc < "0111111111") then
rc <= rc + 1;
else
rc <= "000000000";
end if;
end if;
end process;
end Behavioral;