FourDisplaySevenSegVHDL.vhd

Inputs:

1. clk : designed for 50 mhz clock but can be used with any clock with appropriate changes made to the VHDL source

2. Digit3 : 5 bit bus, lower four bits control the hexadecimal value displayed and the fifth bit controls the decimal point of the display (if equipped) Digit3 controls the Digit associated with driver 3

3. Digit2 - 0 : same as Digit3 above but controls digits 2 - 0

4. InvertDigit : This controller was designed to operate on a wide variety of displays and driving methods, (common anode, common cathode, inverted driving logic)  Setting this bit to a 1 inverts the display outputs.  For example, the Digit "1" is displayed by turning on segment B and segment C.  The non-inverted digit will drive these segments to a logic high voltage to turn them on.  If you have inverting drivers, you would want them to be driven to a logic low voltage.  simply apply a logic high to this bit to invert all digit outputs.

5. InvertDriver : Inverts the logic level to drive to common (anode, cathode) to the display.  Normally to turn a display on, a logic high is presented to that display.  Some pictures of common configurations and their required setup is given below:
   
   

Outputs:

1. SegDriver : drives the segments for the displays.  The bus outputs are given below:
   
   

2. DisplayDriver : controls which display is on. DisplayDriver(3) controls Digit3 and DisplayDriver(0) controls Digit0 etc. etc.

FourDisplaySevenSegVHDL.vhd